The analog-to-digital (A/D) converter is a key component in many electrical reproduction and measurement systems such as high-quality audio systems (including compact disks and digital audio tape) and high-accuracy measurement systems. Typically, in such systems, high converter resolution and speed are required for overall system accuracy.
Conventionally, high resolution, high-speed A/D converters have used either successive approximation or dual ramp conversion techniques to achieve the required accuracy. In converters using the successive approximation technique, an amplifier with a feedback weighting network is used to successively approximate an analog input signal. However, when such converters are fabricated with conventional monolithic integrated circuit technology, it is usually necessary to adjust the weighting network after fabrication by physical trimming. The trimming must be accurate to achieve high conversion accuracy, and, consequently, as the need for higher converter accuracies increases and the size of the circuit decreases, the trimming operation has become more and more difficult.
Converters using the dual ramp conversion technique require components such as integrators, current sources, comparators and sample-and-hold circuits which have both high speed and accuracy. Typically, these circuits utilize switched capacitors to sample and hold the analog input signal. However, with present integrated circuit technology, it is difficult to fabricate a high-accuracy sample and hold circuit because the charge on the sample and hold capacitor leaks through parasitic capacitances and the switch impedances.
Recently, another A/D conversion technique, called sigma-delta conversion, involving a combination of oversampling and noise shaping has been developed to obtain the required accuracy and speed. This latter technique has an advantage over the successive approximation or dual ramp conversion techniques in that it does not require device trimming or high device tolerances while still achieving the required speed and accuracy.
A typical sigma delta system employs a sigma-delta modulator followed by a digital decimation filter. The modulator converts an analog input signal into a pulse density modulated (PDM) single-bit digital output bit stream. The digital filter, in turn, receives this PDM bit stream and generates a multi-bit pulse code modulated (PCM) output.
While this latter technique has advantages in lowering the device tolerance, the digital decimation filter that is required to convert the PDM signal into a PCM signal is highly complex involving many thousands of transistor elements. Consequently, sigma-delta converters have not been economically competitive with successive approximation or dual ramp converters. However, with the advent of competitively-priced VLSI integrated circuit technology, the sigma-delta converter has been greatly reduced in price and can now compete with the other designs.
The general configuration of a typical sigma-delta converter is shown in FIG. 1 and consists of a modulator 102 in series with a digital decimation filter 108. A frequency-band-limited analog input 100 is applied to the modulator where it is sampled by a sampling clock 104 which operates at frequency that is typically many times greater than the Nyquist sampling frequency. For example, for analog signals in the audio signal bandwidth, the sampling clock may be 2-10 MHz. In such a system, the ratio of the actual sampling frequency divided by the Nyquist frequency is called the "oversampling ratio".
In a manner which will be hereinafter described in detail, modulator 102 produces a PDM at its output 106 (pulse-density-modulated means that the average density of the digital pulses in the output bit stream over a given period of time is approximately equal to the mean value of the analog input over the same period of time). The PDM output is a one-bit output stream at the frequency of the sampling clock. In order to reduce the complexity of modulator 102, a very low resolution analog-to-digital converter is often used in the circuit. This, in turn, produces a large amount of "quantization" noise in the modulator output. However, because the modulator frequency shapes this noise, most of the output quantization noise power is located at frequencies outside of the input signal bandwidth.
Conventional quantization noise analysis indicates that the spectral density of the quantization noise is constant from DC up to one-half the sampling frequency. Consequently, it can be easily shown that as the oversampling ratio increases, the amount of noise in a given bandwidth decreases. As the maximum resolution of the converter is dependent on the amount of noise in the PDM output, the resolution of the converter can be increased by increasing the oversampling ratio. Unfortunately, the converter resolution increases only as the log of the sampling frequency and, consequently, high-resolution converters require prohibitively high sampling frequencies if no noise shaping is performed.
Digital decimation filter 108 is essentially a low-pass digital filter which passes signals in the band of interest but cuts off the quantization noise which is out of band. The filter produces a multi-bit PCM output (typically 12-18 bits) at a frequency which is much lower than the incoming PDM bit stream, and consequently, can be viewed as a PDM to PCM converter. During the PDM to PCM conversion, the output frequency may be lowered from the sampling clock frequency to a frequency range close to the Nyquist sampling rate for the analog input frequency range. While such a filter is complex, it is conventional in construction and operation and will not be described further herein.
A more detailed block diagram of a conventional modulator 102 is shown in FIG. 2 wherein the modulator consists of an A/D converter 212 surrounded by a feedback circuit. The feedback circuit includes summing junction 202, filter circuit 204 and a D/A converter 218. In particular, an analog input X(z) at input 200 is provided to sampling switch 201 which samples the input at the frequency of the sampling clock. The output of switch 201 is provided to summing junction 202 and the output of summing junction 202 is, in turn, provided to filter 204 and from there to A/D converter 210. A/D converter 210 is also controlled by sampling clock 212 to convert the analog signal produced by filter 204 to an output PDM digital signal Y(z).
The output Y(z) is fed back by means of line 216 to D/A converter 218 which reconverts the digital output to an analog signal. This analog signal is then applied, via lead 206, to the negative input of summing junction 202. Consequently, unless the output Y(z) is exactly the same as the input X(z), an error signal will be developed by summing junction 202 which will then pass through the loop to correct the output. The operation of the feedback loop causes the digital output Y(z) to oscillate around the value of the analog input with the amplitude of the oscillations constituting quantization noise. In a typical sigma delta modulator, both A/D unit 210 and D/A unit 218 are very coarse converters and may, in fact, consist of single-bit converters. Consequently, the quantization noise introduced into the system by these devices is considerable. However, with certain assumptions, it is possible to treat the quantization noise as if it were produced by a white noise source Q(Z) and added to the output signal at the position of A/D converter 210 a shown by the dotted lines in FIG. 2.
Overlooking the sampled data nature of the modulator for the present time and viewing the circuit as a linear circuit, it can be shown by conventional filter theory that the forward transfer function of such a circuit is given by: ##EQU1##
However, the transfer function from the noise source Q(Z) to the output is given by: ##EQU2##
FIG. 3A is a plot of the signal gain (in dB) versus frequency of the forward transfer function Y(z)/X(z) whereas FIG. 3B is a plot of the quantization noise transfer function Y(z)/Q(z). In accordance with equation (1) above, FIG. 3A the transfer function Y(z)/X(z) appears as a low-pass filter determined by the characteristics G(z) of filter circuit 204. However, as FIG. 3B illustrates the transfer function for the noise Q(z) is that of a high-pass filter. Consequently, the effect of the feedback and filter circuit is to reduce the quantization noise Q(z) power at lower frequencies and increase it at higher frequencies.
If, for example, the cutoff frequency of decimation filter 108 (FIG. 1) is of (shown by the dotted lines in FIGS. 3A and 3B), then for the frequency band between DC and of the input signal as shown by FIG. 3A will not be attenuated whereas the quantization noise (as shown by FIG. 3B) will be highly attenuated.
The configuration suffers from several problems. More particularly, if filter 204 is a first "order" filter, the quantization noise passing through the system is highly correlated so that the oversampling ratio needed to achieve resolution greater than approximately 12 bits is prohibitively large. One prior art method to overcome this problem is to add a small "dither" signal to the input of filter 204. This signal spreads the input signal spectrum over a larger range and de-correlates the quantization noise from the input signal.
Another prior art method to avoid noise correlation and to reduce the amount of quantization noise in the digital filter passband is to either increase the sampling frequency (as mentioned above) or to increase the slope of the noise transfer function in the passband by increasing the "order" of filter 204.
A circuit utilizing a higher order filter is shown in FIG. 4. The modulator shown in FIG. 4 has characteristics similar to FIG. 2 and analog input 400 is provided to a summing junction 402. However, filter 204 shown in FIG. 2 has been split into two single order integrators 404 and 418 joined by a second summing junction 412. The output 406 of summing junction 402 is provided to integrator 404 and the output of 410 of integrator 404 is, in turn, provided to summing junction 412. The output 414 of junction 412 is provided to the second integrator 418. The output 420 of integrator 418 is provided to A/D converter 422 which generates the PDM output 424.
As with the single order modulator, the digital output is fed back, via lead 426, to a D/A converter 428. The output of the D/A converter is provided via leads 408 and 416 to the summing junctions 402 and 412, respectively. This modulator operates in similar manner to that shown in FIG. 2 with the exception that the slope on the noise transfer curve shown in FIG. 3B is steeper in accordance with conventional filter theory.
Higher order sigma delta modulators containing more than two integrators in the forward path theoretically offered the potential of even further increases in resolution. However, it was found that modulators with more than two integrators suffered from instability due to the accumulation of large signals and phase lags in the integrators which tends to reduce the average gain of the quantizer. Consequently, third or higher order modulators with the basic architecture shown in FIG. 4 were not designed because these modulators were marginally stable and it was believed that they would oscillate.
Various alternative approaches, however, have been used to construct higher order modulators. One such scheme is shown in FIG. 5. This circuit uses a second order filter comprised of integrators 514 and 520 combined with both feed-forward and feedback paths to achieve the required noise shaping. In particular, the analog input on lead 500 is provided to a summing junction 502. The output of summing junction 502 is provided to integrator 514 and the output 516 of integrator 514 is, in turn, provided to integrator 520. Summing junction 502 is provided with feedback 510 from the feedback D/A converter 536. However, in addition, the summing junction 502 is provided with feedback from another summing junction 504 which in turn receives feedback from the output of each of the integrators. More particularly, the output of integrator 514 is applied, via lead 518 and amplifier 508, to summing junction 504 and the output of integrator 520 is applied, via lead 522 and amplifier 506, to summing junction 504.
In a similar manner, the outputs of integrators 514 and 520 as well as the output of summing junction 502 are applied to a further summing junction 530 via amplifiers 524-528. The output of this latter summing junction is, in turn, applied, via lead 538, to A/D converter 534 which produces the PDM modulated output 540. The circuit in FIG. 5 is a combination of both an interpolative and a predictive modulator. The feedback signal developed by summing junction 504 acts in an interpolative manner and causes the feedback loop to filter the quantization noise generated by the A/D converter 534. Alternatively, the feed-forward signal developed by summing junction 530 acts as in a predictive manner and causes the output of the feedback loop to predict the input. Any resulting error is quantized and used to make the next prediction.
The filter arrangement shown in FIG. 5 can improve the signal-to-noise ratio of the modulator. However, the configuration requires coefficient summing junctions 504 and 530 at both the input and the output of the circuitry. Thus, either a high-accuracy, high-speed amplifier must be used to implement the summing junctions or the signals must be added by connecting them to a summing capacitor. In the latter case, the outputs are subject to distortions and inaccuracies due to parasitic capacitances in parallel with the summing capacitor.
A third type of prior art circuit is shown in FIG. 6. This circuit utilizes what is known as "MASH" technology. In this arrangement, three first-order sigma-delta modulators (each with a configuration shown in FIG. 2) are cascaded in series and their outputs are summed together to form the final PDM output. In particular, the analog input on lead 600 is applied to a first sigma-delta modulator (SDM) 602. The PDM output 604 is summed with the output of the internal filter circuit P(z) shown in FIG. 2. The error signal developed by summer 606 is provided, via lead 608, to a second first-order SDM 610. The output of modulator 610 (on lead 614) is, in turn, summed with the filter signal P(z) on lead 619 in summer 618. The output of summer 618 is, in turn, provided, via lead 620, to a third first-order SDM 612.
The outputs 604, 614 and 622 of the three SDMs 602-612 are then processed to generate the final output. More particularly, the output of the second SDM 610 is differentiated, via differentiator 616, and applied to summing junction 634 via lead 630. The output 622 of the third SDM 612 is differentiated twice by differentiators 624 and 626 and provided, via lead 632, to summing junction 634. The output of summing junction 634 is summed with the output of SDM 602 on lead 628 in junction 636 to produce the final output 638.
The circuit shown in FIG. 6 has the potential of achieving high resolution since the coarse quantization error produced by the first SDM 602 is successively corrected in each further stage. Unfortunately, this prior art arrangement has two significant problems. In particular, since the output 638 is the sum of several different signals, it is no longer a single-bit signal but rather a multi-bit signal. The multi-bit signal requires more complex processing circuitry in the remainder of the converter (in particular, in the digital filter). Secondly, the outputs of the second and third sigma delta modulators 610 and 612 must be differentiated to combine them. An error will occur if the differentiation is not the precise inverse of the integration implicitly performed by modulators 602 and 610. Since the outputs 614 and 622 of modulators 610 and 612 are digital signals, a near-perfect differentiator can be constructed. Thus, integrator errors will allow quantization noise from SDM 602 and 610 to "leak" into the PDM output (since the noise from these stages is shaped with low order SDM's, it contains appreciable spectral tones).
Accordingly, it is an object of the present invention to provide a sigma delta modulator which has both high-resolution and high speed.
It is another object of the present invention to provide a sigma delta modulator in which the filter order can be increased beyond second order without suffering instability.
It is a further object of the present invention to provide a sigma delta modulator which has reduced complexity and can be easily fabricated by monolithic circuitry.
It is still another object of the present invention to provide a sigma delta modulator in which recovery from transients can be accomplished easily.
It is yet another object of the present invention to provide a sigma delta modulator which can be fabricated using switched capacitor circuitry.
It is still another object of the present invention to provide a digital sigma delta modulator which can be used as a digital noise shaper in a digital digital-to-analog converter.